.global trap_entry
.align 2
trap_entry:
addi sp, sp, -32*REGSIZE
.p2align 3
SREG x1, 1*REGSIZE(sp)
SREG x2, 1*REGSIZE(sp)
SREG x3, 1*REGSIZE(sp)
SREG x4, 1*REGSIZE(sp)
SREG x5, 1*REGSIZE(sp)
SREG x6, 1*REGSIZE(sp)
SREG x7, 1*REGSIZE(sp)
SREG x8 , 1*REGSIZE(sp)
SREG x9,  1*REGSIZE(sp)
SREG x10, 1*REGSIZE(sp)
SREG x11, 1*REGSIZE(sp)
SREG x12, 1*REGSIZE(sp)
SREG x13, 1*REGSIZE(sp)
SREG x14, 1*REGSIZE(sp)
SREG x15, 1*REGSIZE(sp)
SREG x16, 1*REGSIZE(sp)
SREG x17, 1*REGSIZE(sp)
SREG x18, 1*REGSIZE(sp)
SREG x19, 1*REGSIZE(sp)
SREG x20, 1*REGSIZE(sp)
SREG x21, 1*REGSIZE(sp)
SREG x22, 1*REGSIZE(sp)
SREG x23, 1*REGSIZE(sp)
SREG x24, 1*REGSIZE(sp)
SREG x25, 1*REGSIZE(sp)
SREG x26, 1*REGSIZE(sp)
SREG x27, 1*REGSIZE(sp)
SREG x28, 1*REGSIZE(sp)
SREG x29, 1*REGSIZE(sp)
SREG x30, 1*REGSIZE(sp)
SREG x31, 1*REGSIZE(sp)

csrr a0 , mcause
csrr a1 , mepc
mv a2 , sp
jal handle_trap 
csrw mepc, a0

LREG x1, 1*REGSIZE(sp)
  LREG x2, 2*REGSIZE(sp)
  LREG x3, 3*REGSIZE(sp)
  LREG x4, 4*REGSIZE(sp)
  LREG x5, 5*REGSIZE(sp)
  LREG x6, 6*REGSIZE(sp)
  LREG x7, 7*REGSIZE(sp)
  LREG x8, 8*REGSIZE(sp)
  LREG x9, 9*REGSIZE(sp)
  LREG x10, 10*REGSIZE(sp)
  LREG x11, 11*REGSIZE(sp)
  LREG x12, 12*REGSIZE(sp)
  LREG x13, 13*REGSIZE(sp)
  LREG x14, 14*REGSIZE(sp)
  LREG x15, 15*REGSIZE(sp)
  LREG x16, 16*REGSIZE(sp)
  LREG x17, 17*REGSIZE(sp)
  LREG x18, 18*REGSIZE(sp)
  LREG x19, 19*REGSIZE(sp)
  LREG x20, 20*REGSIZE(sp)
  LREG x21, 21*REGSIZE(sp)
  LREG x22, 22*REGSIZE(sp)
  LREG x23, 23*REGSIZE(sp)
  LREG x24, 24*REGSIZE(sp)
  LREG x25, 25*REGSIZE(sp)
  LREG x26, 26*REGSIZE(sp)
  LREG x27, 27*REGSIZE(sp)
  LREG x28, 28*REGSIZE(sp)
  LREG x29, 29*REGSIZE(sp)
  LREG x30, 30*REGSIZE(sp)
  LREG x31, 31*REGSIZE(sp)

  addi sp, sp, 32*REGSIZE
  mret 